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XRD6414
CMOS 10-Bit, 20 MSPS, High Speed Analog-to-Digital Converter ...the analog plus company TM with 4:1 Input Analog Multiplexer
March 1997-3
FEATURES D 10-Bit Resolution D 20MHz Sampling Rate D 4:1 Analog Input Multiplexer D Internal S/H Function D Single 5.0V Power Supply D VIN DC Range: 0V to VDD D VREF DC Range: 1V to VDD D Low Power: 120mW (typ) D Three-State Digital Outputs D Power Down: 1.5mW (typ) Power Dissipation D ESD Protection: 2000V Minimum D For 3V Operation Refer to XRD64L14
APPLICATIONS D Multiplexed Data Acquisition D Precision Scanners D Digital Color Copiers D Test and Scientific Instruments D Digital Cameras D Medical Imaging D IR Imaging BENEFITS D Complete Analog-to-Digital Converter (ADC) that Requires no External Active Components D Small Outline Package to Reduce Board Space D Low Power Dissipation D Easy to Use Rugged Design
GENERAL DESCRIPTION The XRD6414 is a 10-bit, 20 MSPS, Analog-to-Digital Converter (ADC) with a 4:1 Analog Input Multiplexer for applications that require high speed and high accuracy. Designed using an advanced CMOS process, this part offers excellent performance, low power consumption and latch-up free operation. The XRD6414 uses a subranging architecture to maintain low power consumption at high conversion rates. Our proprietary comparator design achieves a low analog input capacitance. The input circuitry of the XRD6414 includes an on-chip S/H function that allows the product to digitize analog input signals between AGND and AVDD. The XRD6414 can be placed into power down (stand-by) mode, reducing the power dissipation to 1.5mW (typical) by a digitally controlled pin. Providing external reference voltages allows easy interface to any input signal range between AGND and AVDD. This also allows the system to calibrate out zero scale and full scale errors by adjusting VRT and VRB. A separate power supply pin, DVDD, sets the output logic levels for 3V or 5V interface. This device operates from a single 5.0V supply. Power consumption from a 5.0V supply is typically 120mW at FS=15MHz. For 3.3V power supply operation refer to XRD64L14.
ORDERING INFORMATION
Operating Temperature Range -40C to +85C
Part No. XRD6414AIQ
Package 32 Lead TQFP (7 x 7 x 1.4 mm)
Rev. 1.00
E1996
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
XRD6414
AVDD(3) AGND(3) DVDD DGND
VRT
Latched MSB Comparators Encoder and Error Correction Latched LSB Comparators 11 F/F
OFW DB9 (MSB)
RL
DB0 (LSB)
VRB VIN AOUT AIN1 AIN2 AIN3 AIN4 THA Clock and Control Logic
4:1 MUX
A1 A0
CLK
PD
OE
Figure 1. Simplified Block Diagram
PIN CONFIGURATION
24
17
25
16
32
9
1
8
32 Lead TQFP (7 x 7 x 1.4 mm)
Rev. 1.00 2
XRD6414
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol DB9 DGND AGND A0 A1 AVDD CLK OE PD AVDD AGND VRT VRB AIN4 AIN3 AGND AIN2 AIN1 AOUT VIN AVDD DVDD OFW DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 Description Data Output Bit 9 (MSB) Ground (Digital Outputs) Ground MUX Select Bit 0 MUX Select Bit 1 Power Supply Sampling Clock Input Output Enable Control Power Down Control Power Supply Ground Top of Reference Ladder Bottom of Reference Ladder MUX Analog Signal Input 4 MUX Analog Signal Input 3 Ground MUX Analog Signal Input 2 MUX Analog Signal Input 1 MUX Analog Signal Output Analog Input Voltage to ADC Power Supply Power Supply (Digital Outputs) Overflow Output Data Output Bit 0 (LSB) Data Output Bit 1 Data Output Bit 2 Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 Data Output Bit 6 Data Output Bit 7 Data Output Bit 8
Rev. 1.00 3
XRD6414
ELECTRICAL CHARACTERISTICS
Unless Otherwise Specified: AVDD = DVDD = 5.0V, FS = 15MHz (50% Duty Cycle), VRT = 5.0V, VRB = 0.0V, TA = 25C
Symbol Key Features n FS DNL INL EZS EFS VINPP Resolution Maximum Sample Rate Differential Non-Linearity Integral Non-Linearity Zero Scale Error Full Scale Error DC Input Range -0.8 -2.5 0 -1.0 AGND 10 20 0.6 1.5 20 0.4 15 1.0 2.5 40 1.0 AVDD Bits MSPS LSB LSB mV % V VIN can swing from AGND to AVDD, actual digitized range is set by VRT & VRB. Best Fit Line (Max INL - Min INL)/2 Parameter Min. Typ. Max. Unit Conditions
DC Accuracy1
Reference Voltages VRT VRB VREF RL Top Reference Voltage Bottom Reference Voltage Differential Ref. Voltage2 Ladder Resistance Input Voltage Range BW CIN CIN RON ROFF TSW Xt tAP tAJ Dynamic SNR SNDR Signal-to-Noise Ratio FIN = 1MHz SNR and Distortion FIN = 1MHz 56 dB FS = 10MSPS 57 dB FS = 10MSPS Input Bandwidth (-1dB)4 Input Capacitance Input Capacitance Switch Impedance Switch Impedance Switching Time Crosstalk Aperture Delay Aperture Jitter Sample5 Convert5 1.0 AGND 1.0 350 VRB 50 20 7 60 10 15 -80 6 30 120 5 2.5 0.5 2 500 AVDD
AVDD-1
V V V V MHz pF pF M ns dB ns ps fIN = 6MHz CLK = low CLK = high VRB min. = AGND VRT max = AVDD
AVDD 650 VRT
Analog Input3
Analog Multiplexer
Conversion Character
Rev. 1.00 4
XRD6414
ELECTRICAL CHARACTERISTICS (CONT'D)
Symbol Digital Inputs VIH VIL IIN Digital Input High Voltage Digital Input Low Voltage DC Leakage Currents6 5 5 mA pF Between AGND and AVDD CLK, OE, PD, A0, A1 Input Capacitance Digital Outputs VOH VOL IOZ tDL tDEN tDHZ Output High Voltage Output Low Voltage High-Z Leakage Data Valid Delay2 Data Enable Delay Data High-Z Delay Pipeline Delay (Latency) Power Supplies IDD(PD) AVDD DVDD IDD Power Down (IDD) Operating Voltage7,8 Logic Power Supply9 4.5 2.7 24 0.3 5.0 0.5 5.5 5.5 32 mA V V mA PD = low PD = high, excluding current through reference ladder -10 10 10 7 12 12 8 3 4.5 0.4 10 14 14 9 V V mA ns ns ns cycles Time delay between CLK and data output OE = high, or PD = high 3.5 1.5 V V Parameter Min. Typ. Max. Unit Conditions
Supply Current (IDD)
Notes 1 Tester measures code transitions by dithering the voltage of the analog input (V ). The difference between the measured and the IN ideal code width (VREF /1024) is the DNL error. The INL error is the maximum distance (in LSBs) from the best fit line to any transition voltage. Accuracy is a function of the sampling rate (FS). 2 Specified values guarantee functionality. Refer to other parameters for accuracy. 3 Guaranteed. Not tested. 4 -1 dB bandwidth is a measure of performance of the A/D input stage (S/H + amplifier). Refer to other parameters for accuracy within the specified bandwidth. 5 See V equivalent circuit. Switched capacitor analog input requires driver with low output resistance. IN 6 All inputs have diodes to AV DD and AGND. Input DC currents will not exceed specified limits for any input voltage between AGND and AVDD . 7 The GND pins are connected through the silicon substrate. Connect all GND pins together at the package and to the analog ground plane. DGND and GND are connected through junction diodes. See logic output interface section. 8 The V DD pins should be tied together at the package. 9 See logic output interface section.
Specifications are subject to change without notice
Rev. 1.00 5
XRD6414
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3 VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V VRT & VRB . . . . . . . . . . . . . . . . VDD +0.5 to GND -0.5V VIN . . . . . . . . . . . . . . . . . . . . . . VDD +0.5 to GND -0.5V All Inputs . . . . . . . . . . . . . . . . . VDD +0.5 to GND -0.5V All Outputs . . . . . . . . . . . . . . . VDD +0.5 to GND -0.5V Storage Temperature . . . . . . . . . . . . . . -65 to +150C Package Power Dissipation Rating to 75C TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW Derates above 75C . . . . . . . . . . . . . . . . . . . 14mW/C Lead Temperature (Soldering 10 seconds) . . +300C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND.
1/FS tPWL tPWH CLK N N+1 N+2 Pipeline Delay tAP Analog Input VIN DATA (DB0-DB9 and OFW) N+1 Sampling Points N-3 N-2
N
tDL N-1 N N+1
Figure 2. XRD6414 Timing Diagram
OE tDHZ DATA (DB0-DB9 and OFW) High Impedance tDEN
Figure 3. 3-State Timing Diagram
Rev. 1.00 6
XRD6414
THEORY OF OPERATION
VIN Analog Input This part has a switched capacitor type input circuit. The input impedance changes with the phase of the input clock. VIN is sampled at the low to high clock transition and the digital data changes at the low to high clock transition. The diagram Figure 4. shows an equivalent input circuit.
AVDD 100 VIN 5pF VRT + VRB + - 2 CLK 1.5pF CL CLK 18pF 100
Power Supply Sequencing There are no power supply sequencing issues if DVDD and AVDD of the XRD6414 are driven from the same supply. Best parametric results, however, are obtained when DVDD and AVDD are driven from separate supplies. When DVDD and AVDD are driven separately, AVDD must come up at the same time or before DVDD, and go down at the same time or after DVDD. If the power supply sequencing in this case is not followed, then damage may occur to the product due to current flow through the source-body junction diodes between DVDD and AVDD. A low threshold schottky diode placed locally between DVDD and AVDD can prevent damage to the XRD6414. Logic Output Interface
AGND
Figure 4. Equivalent Input Circuit
OFW Overflow (Output) This signal indicates when the Analog Input (VIN) goes above VRT. The pin is normally at a low logic level. When VIN > VRT, OFW will go high and the data bits (DB0 - DB9) will show full scale (i.e. all 1s). OE Output Enable (Input) This signal controls the 3-state drivers on the digital outputs DB0 - DB9 and OFW. During normal operation OE should be held low so that all outputs are enabled. When OE is driven high DB0 - DB9 and OFW go into high impedance mode. This control operates asynchronous to the clock and will only control the output drivers. The internal output register will get updated if the clock is running while the outputs are in three-state mode.
OE 0 1 DBO-DB9 Enabled Three-Stated OFW Enabled Three-Stated
The digital output drive circuitry of the XRD6414 was designed to operate separately from the analog supplies. The DVDD pin of the XRD6414 is a separate power supply dedicated to the logic output drivers. DVDD is not connected internally with any of the other power supplies. Figure 5. illustrates the power supply circuity of the XRD6414. DVDD and DGND connect directly to the digital logic power of the user's system isolating the analog and digital power supplies and grounds. DGND is not common to the XRD6414 substrate. The XRD6414 substrate is common only to the packages' AGND pins. Best spectral performance is obtained when DVDD is lowered to 3.3V. See the power supply sequencing section if AVDD and DVDD are powered separately.
Table 1. Output Enable
Rev. 1.00 7
XRD6414
FINAL DESIGN CONSIDERATIONS The XRD6414 can be evaluated with the XRD6414AB application board. Contact your distributor or sales person for delivery. Using the XRD6414AB the following final design considerations can be made. 1. Be generous with analog and digital ground planes. Mirror the ground plane with the supply planes. Use a 5 mil power / ground plane separation if a four layer board can be used. The XRD6414 substrate is common to the packages' AGND pins only. DGND and DVDD are separate supplies dedicated to the output logic drivers of the XRD6414. Connect DGND and DVDD to the power planes of the system's digital logic. 2. Keep high frequency decoupling capacitors very close to the A/D pins and minimize the loop area included so less flux will induce less noise. Use decoupling capacitors in the same locations as on the XRD6414AB. Coupling between logic signals and analog circuitry can easily change a 10-bit system into an 8-bit system or worse. Completely separate them. Watch for coupling opportunities from other sources not immediately associated with the A/D. Don't use switching power supplies in adjacent locations, for example. The DC performance of the XRD6414 is optimized with rise and fall times of CLK edges limited to greater than or equal to 10ns. A resistor in series with the CLK input pin can combine with parasitic capacitance to limit rise and fall times. Select a low jitter clock with a 50% duty cycle for best spectral results. Use support devices equivalent to those used on the evaluation board. Use the application board to verify these devices up front, i.e. use very linear passive components in the signal path. Select a driving op amp whose noise, speed, and linearity fits the application. Use a resistor to decouple 7. the output of the driving op amp from the switching input capacitance of the XRD6414. DNL and INL performance is optimized when the VRB input of the XRD6414 is buffered. If VRB is connected to the PCB ground plane it is subject to the noise and ground bounce in that plane. For example VRB could be buffered to 50mV above ground and still have a wide reference voltage range set by connecting VRT to a voltage near AVDD. Use 50 or 100 resistors to isolate the XRD6414 digital output pins from a latch or bus connection. This protects the output drivers and reduces the effects of high speed switching logic signals from degrading the ADC performance. Layout the latch or digital buffers as close to the ADC as possible to minimize trace length.
8.
3.
AVDD
Source-body junction diode DVDD between DVDD & AVDD
4.
A/D Circuit
DB(0-9) & OFW
5.
AGND
Source-body junction diode between DGND & AGND
DGND
6.
Figure 5. XRD6414 ADC Power Supply Circuit Allows Separate AVDD & DVDD and Separate AGND & DGND
Rev. 1.00 8
XRD6414
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 0 200 400 CODE 600 800 1000 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 0 200 400 600 800 1000 CODE
LSB
Figure 6. XRD6414, DNL @ 15MSPS AVDD = 5V, VRT = 2.5V, VRB = 0.5V
LSB
Figure 7. XRD6414, INL @ 15MSPS AVDD = 5V, VRT = 2.5V, VRB = 0.5V
0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -0.05 -0.01 -0.15 -0.20 -0.25 -0.30 -0.35 0 200 400 CODE 600 800 1000
1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 0 200 400 600 CODE 800 1000
LSB
Figure 8. XRD6414, DNL @ 15MSPS AVDD = 5V, VRT = 5V, VRB = AGND
LSB
Figure 9. XRD6414, INL @ 15MSPS AVDD = 5V, VRT = 5V, VRB = AGND
Rev. 1.00 9
XRD6414
Figure 10. Crossplot Staircase Output CLK = (15MSPS, trf = 15ns), VIN = 3V, VREF = 2V
140 120 100
RON vs. VIN
6.0 AOUT 5.0 4.0 A OUT (V) 3.0 2.0 1.0 0.0 -1.0 A0
R ON ()
80 60 40 20 0 0 1
AVDD = 5V
2 3 VIN (Volts)
4
5
0
10
20
30
40
50 t(ns)
60
70
80
90
Figure 11. Analog MUX RON vs. Input Voltage
Figure 12. MUX Switching Time Waveform, AVDD = 5V
Rev. 1.00 10
XRD6414
A1 0 0 1 1 A0 0 1 0 1 Selected Analog Input AIN1 AIN2 AIN3 AIN4
Table 2. Truth Table for Analog Input Selection
PD 1 0 Device Status Off (Not Operating) On (Operating)
Table 3. Power Down
AVDD (5 V) Crosstalk (dB)
5V or 3V 26pF 10MW AGND JP15 (2,3)
AIN1 AIN2 AOUT VIN XRD6414
A1 A0 50
-78 -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 -102 -104 -106 -108 -110 -112 -114 0.00 2.00 4.00 FIN(MHz) 6.00
Figure 13. MUX Switching Time Test Circuit
Figure 14. XRD6414 Crosstalk, AVDD = 5V and VIN = 8dBm
Rev. 1.00 11
XRD6414
40 30 20 5V VSOURCE VIN 50 AVDD AIN1 XRD6414 VOUT 50 AGND AIN3 A0 AOUT A1 dB 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 0 0.1 0.2 0.3 FIN / FS 0.4 0.5
Figure 15. Crosstalk Test Circuit
Figure 16. XRD6414 FFT VREF = AVDD = 5V, DVDD = 3.3V, FIN = 100kHz, FS = 10MSPS, CIN = 100pF
60 59 58 dB dB 10 100 Input Frequency (kHz) 1,000 57 56 55 54 53
58 57 56 55 54 53 52 51 50 49 10 100 Input Frequency (kHz) 1,000
Figure 17. XRD6414 SNR & SNDR vs. FIN, AVDD = 5V, DVDD = 3.3V, VREF = 5V & 2V, FS = 10MSPS, CIN = 100pF
Figure 18. XRD6414 SNR & SNDR vs. FIN, AVDD = 5V, DVDD = 3.3V, VREF = 5V & 2V, FS = 15MSPS, CIN = 100pF
Rev. 1.00 12
XRD6414
32 LEAD THIN QUAD FLAT PACK (7 x 7 x 1.4 mm TQFP)
Rev. 2.00
D D1 24 17
25
16
D1 D 32 9
1 B A2 e
8
C A Seating Plane A1 L
INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.055 0.002 0.053 0.012 0.004 0.346 0.272 MAX 0.063 0.006 0.057 0.018 0.008 0.362 0.280
MILLIMETERS MIN 1.40 0.05 1.35 0.30 0.09 8.80 6.90 MAX 1.60 0.15 1.45 0.45 0.20 9.20 7.10
0.0315 BSC 0.018 0 0.030 7
0.80 BSC 0.45 0 0.75 7
Note: The control dimension is the millimeter column
Rev. 1.00 13
XRD6414 Notes
Rev. 1.00 14
XRD6414 Notes
Rev. 1.00 15
XRD6414
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 1996 EXAR Corporation Datasheet March 1997 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 1.00 16

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